1. Field of the Invention
The invention relates generally to the fabrication of semiconductor components such as integrated circuits. More particularly, the invention relates to (1) processes for fabricating delamination resistant multi-layer lift-off stencils; (2) delamination resistant multi-layer lift-off stencils per se, whether a product of the aforementioned processes or created by alternative techniques; and (3) methods for applying metalized interconnections to a lift-off structure that includes a stress relief (or "cushioning") layer as part of the lift-off stencil.
The invention is particularly useful in situations where it is desirable to deposit several microns of metal on a substrate, where high stress metals (like nickel) are to be deposited and/or in situations where multiple evaporation steps are required to fabricate a semiconductor component.
2. Description of the Related Art
Many recent patents and technical articles have been directed to advances in the field of semiconductor component fabrication using improved materials and processes. Such improved materials and processes have been useful in meeting increasingly demanding requirements for advanced integrated circuit fabrication, particularly those integrated circuits that include high density interconnective multi-level metallurgy systems.
As an example of the aforementioned advances, U.S. Pat. No. 4,692,205, to Sachdev et al, issued Sep. 28, 1987, assigned to the International Business Machines Corporation, teaches the use of what was then a new material, silicon-containing polyimides, as an oxygen etch barrier in a metal lift-off process and as an oxygen etch stop in the fabrication of multi-layer metal structures.
U.S. Pat. No. 4,692,205 is hereby incorporated by reference, not only for the its specific teaching of silicon-containing polyimides as an oxygen etch barrier, etc., but also for its review of lift-off processes in general and its teaching of exemplary commercially available chemicals that may be used in fabricating various layers of the stencil structure to be described hereinafter.
More particularly, the aforementioned reference describes a lift-off method for fabricating fine metal lines in a process that requires contacting films to maintain mechanical and interfacial integrity. However, the processes described in the incorporated reference do not maintain the desired mechanical and interfacial integrity of film layers in stencils used to fabricate semiconductor components in situations where high stress metals (such as nickel) are used, or in situations where multiple step metallization processes need to be performed. Multiple step metallization processes are, for example, often performed when multi-level metallurgy systems require different metal thickness on the same substrate.
A specific problem encountered in semiconductor component fabrication processes utilizing high stress metals and/or multiple step metallization processes, is the delamination of interfacing films. Such delamination destroys the stencil structure being used to fabricate a semiconductor component and can significantly decrease the yield of acceptable components, making delamination an undesirable characteristic of prior art lift-off techniques in general (including the one taught in the incorporated reference), for which it is presently desirable to find a remedy.
To be more specific, well known lift-off methods for forming metallized structures, such as the one taught in the incorporated reference, involve the fabrication of a multi-layer stencil comprising a solvent removable polymer film as the base or lift-off layer on a substrate. This lift-off layer is sequentially overcoated with a thin oxygen reactive ion etch (RIE) barrier and a resist layer.
The desired pattern in the resist layer can be delineated by standard lithographic techniques and then replicated into the underlying RIE barrier layer by the RIE process using carbon tetrafluoride (CF.sub.4) ambient, followed by an oxygen plasma to etch the pattern into the lift-off layer. Subsequent blanket metal evaporation and solvent soak (e.g., N-methyl-pyrrolidone (NMP)) is employed to accomplish the removal of the lift-off stencil, leaving the desired metal pattern intact on the substrate surface.
Conventional oxygen RIE barrier films, such as plasma polymerized organosilicon HMDS (hexamethyldisilazane) suffer adhesion problems when high stress metal is (or metals are) evaporated and/or multiple evaporation steps are used to have different metal thickness deposited on the substrates.
When multiple evaporation steps are used the lift-off stencil is thermally stressed even more because, for example, a stencil covered with high stress blanket metal is heated and cooled in an evaporator during each subsequent evaporation step to achieve a desired metal thickness. Adhesion between the RIE barrier and the organic polymer is then sometimes insufficient to withstand process induced stress and thermal stress created by the difference of thermal coefficient of evaporated metal/RIE barrier and organic polymer.
The result is that the interfacial integrity of film layers in stencils used to fabricate semiconductor components in situations where high stress metals and/or multiple step metallization processes are used are prone to suffer from the aforementioned undesirable delamination characteristic.
Accordingly, it would be desirable to provide a multi-layer delamination resistant lift off stencil that can withstand the stresses induced by high stress metals, the deposition of relatively "thick" (several micron) layers of metal, and thermal stress introduced by multiple evaporation steps.
Furthermore, it would be desirable to provide processes for fabricating such a stencil as part of a novel lift-off structure and to provide methods for utilizing such a structure to perform both single and multiple step metallization processes in general.
Still further, it would be desirable to provide improved materials and processes for depositing different thickness of metal on a substrate to facilitate the fabrication of advanced integrated circuits that specifically include high density interconnective multi-level metallurgy systems.